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Return to: 2010 Feature Stories

CLIENT: IMAGINATION TECHNOLOGIES

May 2010: IP Designer & Integrator

DESIGNING THE SOCCER SYSTEM ON CHIP

Having developed a broad range of highly complex, fully synthesisable semiconductor IP cores IP over many years, Imagination Technologies has evolved a comprehensive approach to the architecture and implementation of high performance, low power SoCs (Systems on Chip). This both helps its licensees reduce time to market and risk and also helps Imagination to create its own SoC designs -- both for customer-specific designs and for test chips.

ImgTec

Imagination faced a number of challenges when implementing the latest customer-specific SoC design, code-named “SoCcer” – a device designed to address a wide array of communications and Linux-hosted embedded processing and audio DSP functions in a single, low cost SoC.

The SoCcer project was born from two needs. Imagination’s IMGworks group wanted to create a reference SoC design that demonstrates to our customers and partners how  to integrate the IP building blocks and key architectural concepts championed inside Imagination to ensure that all of Imagination’s META processor and ENSIGMA communications IP cores work well together in a system as well as individually. Meanwhile, the PURE division of Imagination, which designs and manufactures a range of digital radio and connected audio products based on Imagination’s ENSIGMA and META IP cores using SoCs from some of Imagination’s licensees, was keen to utilise their experience to help IMGworks create a design for a  next generation SoC device that would better meet their future needs.

This project was to prove one of the most demanding ever undertaken by Imagination’s IMGworks SoC design, integration and layout teams. With a total timescale from design start to fully operational demonstrations of only 15 months, including three months fab cycle time, full software bring-up and an extensive RF integration tasks for multiple radios once silicon was received from the foundry, this was a demanding exercise that would test the limits of their knowledge gained from more than 20 previous SoC design and implementation projects.

API-based Heterogeneous Software Integration

The SoCcer architecture builds on Imagination’s concept of heterogeneous computing, which is based on the principle that any SoC should comprise a series of co-operating processor engines, each optimised for the application domain in which it is operating. For SoCcer, that meant that two highly specialised VLIW communications engines were combined with one multi-threaded 32-bit processor that handled both the general-purpose Linux-based processing as well as highly optimised audio DSP tasks. Each of these application domains requires a different software environment, yet all these software and hardware domains must work efficiently together to make a total solution.

Imagination’s IP cores each come with their own comprehensive set of software, which meant that many of the software building blocks were already completed. However, all the software components needed to be brought together on one chip for the first time, from low level drivers to operating systems to high level applications. This was achieved by testing all software components on other silicon platforms, then using well-defined APIs to bring them all together on the SoC. The success of this approach demonstrates clearly that if well defined APIs are used as the basis of the architecture of an SoC device, complex software integration can be far less of a problem than many anticipate.

After initial testing when the chip returned from fab, one of the first elements to be brought up was the Linux OS kernel. It was a major milestone that within one week of receiving first silicon, the chip was successfully booting Linux and running test applications, even though this was the first time we had implemented in silicon our 2nd generation high performance META HTP processor core. All the simulations to get to this point were indeed correct!

3rd Party Process specific IP

Since this device was a customer production quality chip, it was important to use a mainstream 65nm low power process where sufficient external IP was available to meet the needs of a highly integrated system, including:

  • high speed ADCs and DACs for IF interfacing
  • flexible high performance memory compilers
  • suitable I/Os for high speed, low power operation
  • PLLs for on-chip clock generation and synchronisation

Sourcing the additional IP blocks needed to deliver the required performance and low power proved almost as challenging as the design itself, as different IP was available for different processes, but often IP vendors had off the shelf solutions that never quite met all the specifications required, or targeted different processes. Also, it was important to be first-time right in order to meet tough timescale constraints for demonstrations at major trade shows. Fortunately, the IMGworks team identified one vendor of ADCs and DACs that was willing to adapt their designs to Imagination’s exact specifications and process in the available timescales. Other IP blocks were sourced from proven partners who had worked with Imagination in the past with good records of success.

Hardware Architecture

Another major challenge was the design of the underlying SOC system bus infrastructure to be used. As is Imagination’s design practice, everything is designed to be re-used, so not only was a new solution designed, but compilers and tools also developed to abstract it for future SoC designs, that could take into account not just the aggregate, average and peak data bandwidth requirements, but also the likely burst traffic scenarios expected in the SoC under real operating conditions.

SoCcer’s communications capabilities, a key feature of the device, are built on its dual ENSIGMA UCCP310 multi-standard communications cores. These devices give Imagination the ability to demonstrate the new 3rd generation UCCP310 communications engines which can now transmit as well as receive for standards like 802.11 Wi-Fi, so that a wide range of bidirectional communications can be implemented as well as broadcast receivers. To do this, the VLIW-like complex vector processor architecture was complemented with additional dataflow engines to enable data to flow in both directions. SoCcer also enabled Imagination to demonstrate for the first time the benefits of having multiple tuners on the same SoC – for example a reconfigurable combination of Wi-Fi communications and TV receivers at the same time.

Tension was high during commissioning of the first bi-directional modem – 802.11 a/b/g. Not only was this the first time the UCCP was executing bidirectional modem code, but also a new RF tuner for Wi-Fi was being used for the first time. Fortunately, the FPGA system on which the non-real time engineering had been done proved to be a reliable baseline platform, and the system leapt into life on schedule.

The SoCcer project has brought together one of the largest multi-disciplinary teams at Imagination, and resulted in major steps forward in the ability for Imagination to promote its total systems concepts as well as some of its latest IP cores. No amount of powerpoint or simulation compares to engineers seeing real silicon executing key high performance functions in real-time, especially when it comes to functions like Wi-Fi or ATSC, or running the latest version of Linux and native audio DSP at the same time in a hardware multi-threaded environment. As a result of this project, SoCcer is therefore proving to be a major boost to Imagination’s demonstration and customer engagement arsenal.

Return to: 2010 Feature Stories