Esperanto Technologies Plans Energy-Efficient Chips for Artificial Intelligence and Machine Learning, based on the open RISC-V standard

First public technology disclosure from stealth start-up at 7th RISC-V Workshop

MOUNTAIN VIEW, CALIF., Nov. 28, 2017 – Esperanto Technologies president and CEO Dave Ditzel today made the first public disclosure of Esperanto's development of energy-efficient computing solutions for Artificial Intelligence (AI) and Machine Learning applications based on the open standard RISC-V Instruction Set Architecture (ISA). During his presentation at the 7th RISC-V Workshop, "Industrial strength high-performance RISC-V processors for energy-efficient computing," Ditzel unveiled the company's plans to deliver RISC-V based computing solutions that will achieve both the highest levels of performance and energy-efficiency for artificial intelligence and machine learning applications.

"Esperanto's goal is to make RISC-V the architecture of choice for the most demanding AI and machine learning applications which will drive computing innovation for the next decade," said Ditzel. "By designing in leading-edge 7nm CMOS and with the simplicity of the RISC-V architecture, we can fit over four thousand full 64-bit cores each with vector accelerators on a single chip. By basing our chip on RISC-V we can take advantage of the growing software base of operating systems, compilers and applications. RISC-V is so simple and extensible that we can deliver world class TeraFlop levels of computing without needing to resort to proprietary instruction sets, thereby greatly increasing software availability."

In his workshop presentation, Ditzel disclosed an overall technology direction for Esperanto's first System-on-Chip designs, including:

Artificial Intelligence supercomputer-on-a-chip designed with leading edge 7nm CMOS
16 "ET-Maxion" 64-bit RISC-V cores for highest single thread performance
4096 "ET-Minion" energy-efficient RISC-V cores each with vector floating point unit
Based on the 64-bit open and free RISC-V Instruction Set Architecture

During his talk, Ditzel also noted that in addition to selling its AI supercomputer chip, the company will license its high-performance ET-Maxion and ET-Minion cores to help proliferate the RISC-V architecture.

"There is considerable industry interest in licensing the high-performance and energy-efficient cores we are developing," noted Ditzel. "As a start-up, we are very focused on addressing our target markets with our AI chip, but we also want to help build the RISC-V ecosystem. We think that by licensing the cores we have in development, we can do both."

Western Digital's CTO Martin Fink announced during his keynote speech at the workshop that Western Digital had made a strategic investment in Esperanto. Western Digital's leadership role in the RISC-V initiative is significant in that it aims to accelerate the advancement of the technology and the surrounding ecosystem by transitioning its own consumption of processors – over one billion cores per year – to RISC-V.

Esperanto's president and CEO Dave Ditzel is well known for founding and taking public the energy efficient processor company Transmeta, as well as his leadership work on the SPARC architecture at Sun Microsystems. Earlier in his career, Ditzel helped launch the RISC processor movement of the early 80's when he co-authored "The Case for the Reduced Instruction Set Computer" with U.C. Berkeley computer science professor David A. Patterson. Before founding Esperanto, Ditzel spent six years at Intel leading various high-performance processor-related projects.

For more information on the RISC-V Foundation and the 7th RISC-V workshop, please visit https://riscv.org/.

About Esperanto Technologies

Esperanto Technologies develops high-performance, energy-efficient computing solutions based on the open standard RISC-V ISA. Esperanto is headquartered in Mountain View, California with engineering sites in the United States, European Union, and Eastern Europe. Esperanto has brought together a seasoned team of experienced processor and software engineers with the goal of making RISC-V the architecture of choice for compute-intensive applications such as Machine Learning. For more information, please visit https://esperanto.ai.

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