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CLIENT: ESPERANTO TECHNOLOGIES
May 7, 2018: eeNews Europe
Startup processor developer Esperanto Technologies Inc. (Mountain View, Calif.) is making use of the analytics IP from UltraSoC Ltd. (Cambridge, England) within its artificial intelligence chip that is projected to contain more than 4,000 64bit processor cores on 7nm manufacturing technology.
Dave Ditzel, founder and CEO of Esperanto, described the work with UltaSoC as collaborative design. "Esperanto’s goal is to make RISC-V the architecture of choice for the most demanding AI and machine learning applications," he added in a statement. "Developing and debugging software utilizing thousands of RISC-V cores will be easier with the advanced analytics that UltraSoC's IP will provide."
It remains unclear when the superchip will emerge from Esperanto or whether it will make use of extreme ultraviolet lithography. "We haven't announced which [7nm] process we're on at TSMC," Ditzel told eeNews Europe in an interview.
It is thought that TSMC's earliest users of 7nm will forego EUV lithography. A second generation of 7nm will attempt to speed production, reduce cost and improve yield by replacing some key quad-patterned immersion layers with EUV lithography layers.
"TSMC is in production with 7nm and there are lots of design tape outs. Exactly which variant of 7nm we will use will be announced." Similarly, Ditzel said Esperanto, founded in 2014, has not announced a timetable for the delivery of its 4k chip to customers. "We're still in the design process and we've been at it for a couple of years," he said.
"We're targeting the datacentre for large scale deployment of machine learning applications. But the solution fits in with desktop and tablet computers. Smartphones are not the target for the first chip but the basic architecture is applicable to cell phones and we are also licensing our technology," Ditzel said.
This holds out the intriguing prospect down the line of Esparanto processing fabric being licensed into smartphone application processors. But for now Esperanto is aiming high.
"Esperanto is aiming at the highest performance at the leading edge; a flagship chip provider for RISC-V." Does that mean we should expect a giant die size? "It's big but not crazy big. We're working with datacentre customers to determine the best trade-offs," answered Ditzel.
"There is a large amount of memory on our die. That is part of the reason we are on 7nm. There's memory and logic on die and memory off die. But Esperanto RISC-V is fairly conventional design. It is what design center software developers are used to. There is a sophisticated memory hierarchy. They are used to that with x86. It is all about supporting high sustainable throughput," said Ditzel.
"We love the extensibility of RISC-V. We used extensions for machine learning and for graphics. Machine learning is very parallelizable. Dataflow graph and partition across thousands of cores and its seems to scale. The popular datatypes are 32 and 16bit floating point and scaled integers at 8bit and 16bit."
"But with 1,000s of cores on a chip but it does mean we have to get them debugged. UltraSoC was by far the strongest to give us meaningful support."
UltraSoC is providing such features as transaction-level bus and status monitoring and static instrumentation to monitor program and execution flow. Such features are part of a broader UltraSoC product offering that supports all industry-standard processor architectures, and supports heterogenous multicore and many-core designs.
Rupert Baines, CEO of UltraSoC, added: "We wanted to provide a standard design and debug ecosystems. It's a new architecture but it has to be made easy to use. We are already capable of multicore support but this is a new scale of multicore. So with processors operating at gigahertz frequency there is a huge amount of raw data. It is up to us to find the information that is meaningful. To act as a bridge to the world of tools and IDEs.
UltraSoC has taken a leading role within the RISC-V Foundation and provides the industry’s first – and still only – commercial RISC-V debug solution.
Return to: 2018 Feature Stories