Feature Story

Designing SoCs – the Agonies and the Ecstasies

Imagination Technologies creates and licenses semiconductor intellectual property (IP) processor cores for graphics, video, multi-threaded embedded processing/DSP and multi-standard communications applications. These products are complemented by software tools and drivers as well as developer and middleware ecosystems. The company recently embarked on the development of an advanced system-on-chip for one of its customers that could also be used to promote its IP and for technology evaluation by its consumer products division, PURE. The design flow and strategies Imagination used to create this device, SoCcer, are described in the article.

Imagination Technologies develops highly complex, fully synthesizable semiconductor cores addressing a wide array of multimedia, communications and embedded processing/DSP functions. Having developed such intellectual property (IP) over many years, it has evolved an advanced, comprehensive approach to the architecture and implementation of high-performance, low-power system-on-chips (SoCs) to help its licensees lower risk and time-to-market, and also to help Imagination create its own SoC designs for test chips and customer-specific projects.

This article explores some challenges the company’s design teams faced when implementing Imagination’s latest customer-specific SoC design, referred to here as ‘SoCcer’, which was demonstrated at the 2010 Consumer Electronics Show (CES).

The requirements

The various design teams within Imagination’s technology division (which develops all of its semiconductor IP products) work closely to maximize the reuse of IP building blocks and develop architectural concepts so that all of the company’s cores work well both individually and together within a system.

Recently, the PURE division of the company (which designs and manufactures a range of digital radio and connected audio products) was looking into ways in which it could drive the evolution of a new generation of SoCs to meet its future needs.

As a result of these two complementary goals, the SoCcer project was born.

The purpose of the SoCcer SoC (Figure 1) was to bring together a number of key features available from Imagination’s IP portfolio in silicon that delivered low power consumption and high performance in an aggressive die area. Foremost among the project’s objectives were:

Figure 1
SoCcer block diagram. Source: Imagination Technologies

implementation of two of the company’s latest ENSIGMA UCCP310 cores on the same chip to demonstrate their Wi-Fi and multi-standard broadcast reception capabilities, as well as the option to reconfigure either core for any of a wide range of TV, radio, mobile TV or Wi-Fi standards so that new system concepts can be explored;
use of two UCCP310 cores together in diversity mode for weak signal reception, and to allow flexibility when implementing advanced diversity methodologies (see box);
use of the company’s latest META HTP hardware multi-threaded 32bit processor/DSP core to run both single-threaded and SMP Linux as well as other combinations such as Linux + RTOS for audio-intensive applications;
implementation of an advanced SoC infrastructure that would enable the effective interaction of deeply embedded META MTX 32bit processors in each UCCP310 core with the central META HTP processor; and
introduction of a switching capability that would enable direct coupling of the central META HTP processor to the ENSIGMA UCC communications engines in some operating configurations.

This project proved to be one of the most demanding ever undertaken by Imagination’s IMGworks SoC design, integration and layout team. The target time-to-delivery—from design start to fully operational demonstration—was just 15 months. This included a three-month fab cycle, full software bring-up and extensive RF integration after silicon had come back from the foundry. Success would depend heavily on exploiting knowledge the team had gained across more than 20 previous SoC designs and implementations.

Getting the right ingredients

Since the device had to be a customer production quality chip, it was important to use a mainstream 65nm low power process where sufficient external IP was available to meet the needs of a highly integrated system. Such IP included:

high-speed analog-to-digital converters (ADCs) and digital-to-analo converters (DAGCs) for IF interfacing;
flexible high-performance memory compilers;
suitable I/Os for high-speed, low-power operation; and
PLLs for on-chip clock generation and synchronization.

Sourcing the additional IP blocks that met requirements for performance and power proved almost as challenging a task as realizing the design itself. Different IP blocks were available for different processes, but often IP vendors’ off-the-shelf solutions did not quite meet the specifications required. The need to have the production-ready device available for the customer’s use at major trade shows on fixed dates also meant that the design had to be first-time right.

Fortunately, the IMGworks team found a vendor of ADCs and DACs that was willing to adapt its designs to Imagination’s exact specifications and process. Other IP blocks were sourced from proven partners who had worked with Imagination in the past with good records of success.

More than just joining the dots

Another major challenge was the design of the underlying SoC system bus infrastructure to be used. Imagination’s philosophy is that everything should be designed so that it can be reused. So, not only was a new solution designed, but compilers and tools were also developed to abstract it for future SoC projects. These account for not only the aggregate, average and peak data bandwidth requirements, but also the likely burst traffic scenarios expected in the SoC under real operating conditions.

EDA tool challenges

SoCcer was implemented in a 65nm low-power process that was optimal in terms of cost, power and IP availability. A multi-vendor flow was used to deliver ‘best in class’ results for each part of the design process. This caused some pain, particularly with regard to interoperability across and between proprietary standards (e.g., the rival CPF and UPF power formats), but we found that we were rewarded with an excellent overall result for working around those issues.

Key features of the design methodology were:

assertion-based verification using formal checking;
directed random verification;
plan-driven verification using coverage metrics;
full chip emulation;
full system FPGA prototyping;
scan compression;
hierarchical power domain insertion;
hierarchical constraint generation and budgeting;
multi-corner, multi-mode optimization; and
dynamic IR drop modeling and back annotation into STA.

This methodology required a significant investment to develop, but the payback was a very rapid chip bring-up with basic function tests running within days of receiving silicon, and no functional bugs. Production test features were made accessible through JTAG, so we were able to run scan vectors, memory BIST, and analog IP testing in the lab from day one to screen the parts.

Embedded processor as peer

Another key concept in Imagination’s approach to SoC design is that the CPU should be regarded as a peer to the other major engines, such as those performing communications, graphics or video tasks. The company is a great believer in using hardware multi-threading to ensure that embedded processors are able to perform the maximum possible amount of work in a unified memory environment, minimizing the number of stalled processor cycles.

For SoCcer, this meant ensuring that the CPU could operate efficiently as a general-purpose Linux application host, while executing heavy-duty audio DSP processing and co-existing with the data rates resulting from two communications engines, each capable of generating transport streams at 30Mbit/s or higher.

Here, the hardware multi-threaded architecture of the META HTP processor came into its own, ensuring that the processor was always working even when high-bandwidth memory traffic from both of the UCCP310 communications engines was in full flow. This enabled the designers to ensure that the processor would be able to run key applications that use a lot of processor bandwidth without compromising the real-time demands of the communications engines.

Software at all levels

The SoCcer architecture builds on Imagination’s concept of heterogeneous computing, which is based on the principle that any SoC should comprise a series of cooperating processor engines, each optimized for the application domain in which it is operating. For SoCcer, it meant that two highly specialized communications engines were combined with one multi-threaded processor that handled both the general-purpose processing and also highly optimized audio DSP processing. Each of these application domains requires a different software environment, yet all of these software domains must work efficiently together for a total solution.

Imagination’s IP cores each come with their own comprehensive set of software, which here meant that many of the software building blocks were already completed. However, all the software components needed to be brought together on one chip for the first time, from low-level drivers to operating systems to high-level applications. This was achieved by testing all the software components on other silicon platforms, then using well-defined APIs to bring them together on the SoC.

After initial silicon testing when the chip returned from the fab, one of the first elements to be brought up was the Linux OS kernel. It was a major milestone that within one week of receiving first silicon, the chip was successfully booting Linux and running test applications. As ever, given Imagination’s heritage in graphics and gaming, it was inevitable that one of those initial test apps was Doom!

Communications—a key component

SoCcer’s important communications capabilities are built on its dual ENSIGMA UCCP310 multi-standard communications cores. Each of these can be reconfigured within a few hundred milliseconds to demodulate all major TV standards (e.g., DVB-T, ISDB-T, ATSC), radio standards (e.g., DAB+, FM), or mobile TV standards (e.g., DVB-H, ISDB-T 1seg or T-DMB). This capability has been proven using earlier generation Series2 UCCP IP cores in a range of SoCs shipping from several silicon vendors. However, this chip was the first to feature Series3 UCCP’s latest feature: bidirectional communications (Figure 2).

Figure 2
ENSIGMA UCCP310 multi-standard communications core. Source: Imagination Technologies

For the first time, UCCP engines can now transmit as well as receive, so that a wide range of bidirectional communications can be implemented as well as broadcast receivers. To do this, the VLIW-like complex vector processor architecture has been complemented with additional dataflow engines to enable data to flow in both directions.

Tension was high during commissioning of the first modem—802.11 a/b/g. Not only was this the first time the UCCP was executing bidirectional modem code, but a new RF tuner for Wi-Fi was also making its debut. Fortunately, the FPGA system on which the non-real-time engineering had been done proved to be a reliable baseline platform and the system leapt into life on schedule.

It wasn’t all straightforward

What was not anticipated, however, was the need for our brand new Wi-Fi link to work in the madness of the CES show floor environment, live at an event that attracts more than 100,000 attendees and hundreds of technology companies as exhibitors. As the real-time video transfer demo first leapt into life on our stand, the data rate gradually degraded as other exhibitors switched on their Wi-Fi networks, as there were many more collisions and backoffs that we had expected.

However, thanks to an intense amount of late night debugging across time zones both in the U.K. and the U.S., the problem was identified as a system configuration issue. Once this was fixed, the demo was a major success thanks to some intensely focused system engineering—and intelligent negotiation across the hardware-software divide.

System integration—designing for system bring-up

Many teams at Imagination came together to bring the SoCcer-based applications to life in an extraordinarily short period of time. They all used Imagination’s CODESCAPE tools, which allow concurrent debugging of all the META processor threads (one two-threaded HTP processor plus two further single-threaded MTX processors) alongside two UCCP310 MCP processors—a total of six simultaneous processing execution domains.

CODESCAPE always supported multi-threaded code development, but over recent years has been extended to accommodate multiple processor architectures in a heterogeneous SoC processing environment. As a result, engineers can now debug both the META and the ENSIGMA MCP processors within the same environment. This means they can tackle many system integration tasks within a common environment, leading to more effective cooperation across engineering teams.

Conclusion

SoCcer brought together one of the largest multi-disciplinary teams at Imagination, and resulted in a major step forward in the company’s ability to promote its total systems concepts as well as some of its latest IP cores. Engineers demand to see real-time operation for many functions, especially when it comes to communications. SoCcer is proving to be a major addition to Imagination’s demonstration arsenal.

SoCcer is an early example of a concept Imagination calls the ‘Connected Processor,’ where we believe any embedded processor must have closely coupled multi-standard configurable communications to enable it to communicate with the Internet and any other broadcast or wireless device at any time anywhere.

The concept goes far beyond the chip itself, with a new comprehensive Web portal offering also being developed as an integral part of every connected processor. One early example of this portal is already used by Imagination’s PURE division to power its Wi-Fi connected audio and Internet radio products.

Thanks to SoCcer, Imagination’s customer is now able to exploit the power of these concepts, and the company itself can demonstrate that they really work in a production quality device. It also is a powerful tool to satisfy an ever demanding engineering community that Imagination really does know how to put its own IP cores and technologies together into production quality SoCs, thus significantly reducing the perceived risk for Imagination’s customers, and further helping them to minimize their time-to-production.

Imagination Technologies Ltd.
Imagination House
Home Park Estate
Kings Langley
Hertfordshire
WD4 8LZ

T: +44 (0)1923 260511
W: www.imgtec.com

About the Authors

Tony King-Smith is marketing VP for the Technology Division at Imagination Technologies, and has previously held senior engineering management roles at Panasonic, Hitachi, LSI Logic and INMOS.

Mark Dunn is an engineering VPs for Imagination Technologies’ IMGworks.

Martin Woodhead is an engineering VPs for Imagination Technologies’ ENSIGMA design team.

Jim Whittaker is an engineering VPs for Imagination Technologies’ META design team.

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